  -----------------------------------------------------------------------------
  -- RTL model
  -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package custom_types is
  type bus16x32 is array(15 downto 0) of std_logic_vector(31 downto 0);
  type in_pipeline_stage is record
    A 	: std_logic_vector(31 downto 0);
    B 	: std_logic_vector(31 downto 0);
    Op  : std_logic_vector(3 downto 0);
  end record in_pipeline_stage;
  type out_pipeline_stage is record
    outLine 	: bus16x32;
	Op  : std_logic_vector(3 downto 0);
  end record out_pipeline_stage;
end package custom_types;
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity FA is
  port(
    A: in std_logic;
    B: in std_logic;
    Cin: in std_logic;
    S: out std_logic;
    Cout: out std_logic
  );
end FA;

architecture rtl of FA is
  begin
    S <= A xor B xor Cin;
    Cout <= (A and B) or (B and Cin) or (A and Cin);
end architecture rtl;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity testbench_FA is
end testbench_FA;

architecture behavioral of testbench_FA is
  signal A,B,Cin,S,Cout: std_logic:= '0';
  begin
    test_FA: entity work.FA(rtl) port map( A, B, Cin, S, Cout);
    
    process is
      begin
        A <= '0';
        B <= '0';
        Cin <= '0';
        wait for 1 ns;
        if S/= '0' or Cout /= '0' then 
          ASSERT false
          REPORT " FA 000 error"
          SEVERITY failure;
        end if;

        A <= '0';
        B <= '1';
        Cin <= '0';
        wait for 1 ns;
        if S/= '1' or Cout /= '0' then 
          ASSERT false
          REPORT " FA 010 error"
          SEVERITY failure;
        end if;

        A <= '1';
        B <= '0';
        Cin <= '1';
        wait for 1 ns;
        if S/= '0' or Cout /= '1' then 
          ASSERT false
          REPORT " FA 101 error"
          SEVERITY failure;
        end if;    

    
        A <= '1';
        B <= '1';
        Cin <= '1';
        wait for 1 ns;
        if S/= '1' or Cout /= '1' then 
          ASSERT false
          REPORT " FA 111 error"
          SEVERITY failure;
        end if;
      end process;
    end architecture behavioral;        
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity RCA is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  Cin : in std_logic;
  Sum : out std_logic_vector(31 downto 0);
  CO  : out std_logic;
  V   : out std_logic
);
end RCA;

architecture rtl of RCA is
  signal c: std_logic_vector (32 downto 0);
  begin
    c(0) <= Cin;
    rippleAdd: for i in 0 to 31 generate
      cellFA: entity work.FA port map (A=> A(i), B=>B(i), Cin=>c(i), S=>Sum(i), Cout=>c(i+1));
    end generate rippleAdd;
    CO <= c(32);
    V <= c(32) xor c(31);
end architecture rtl;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_RCA is
end entity testbench_RCA;

architecture behavioral of testbench_RCA is
  signal A,B,S : std_logic_vector (31 downto 0);
  signal Cin,Cout,V: std_logic;
  begin
    rippleAdder: entity work.RCA(rtl) port map (A,B,Cin,S,Cout,V);
      testSequence: process is
      begin
        A <= std_logic_vector(to_signed(15,32));
        B <= std_logic_vector(to_signed(15,32));
        Cin <= '0';
        wait for 1 ns;
        if to_integer(signed(S))/= 30 or Cout /= '0' or V/= '0' then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
        A <= std_logic_vector(to_signed(15,32));
        B <= std_logic_vector(to_signed(-15,32));
        Cin <= '0';
        wait for 1 ns;
        if to_integer(signed(S))/= 0 or Cout /= '1' or V/= '0' then 
          ASSERT false
          REPORT " RCA 15-15 error 0"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SLTU is
port(
  CO  	 : in std_logic;
  Cout   : out std_logic_vector(31 downto 0)
  
);
end SLTU;

architecture rtl of SLTU is
  begin
    Cout <= (31 downto 1 => '0') & (CO);
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity SLT is
port(
  MSB  	 : in std_logic;
  V  	 : in std_logic;
  Cout   : out std_logic_vector(31 downto 0)
);
end SLT;

architecture rtl of SLT is
  begin
    Cout <= (31 downto 1 => '0') & (((not MSB) AND(not V))or(MSB AND V) );
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_SLTU is
end entity testbench_SLTU;

architecture behavioral of testbench_SLTU is
  signal A,B,S,outs : std_logic_vector (31 downto 0);
  signal Cin,CO,V: std_logic;
  begin
    rippleAdder: entity work.RCA(rtl) port map (A,B,Cin,S,CO,V);
	SetLTU: entity work.SLTU(rtl) port map (CO,outs);
      testSequence: process is
      begin
        A <= "11001011100000010000110010111111";--2comp of "00110100011111101111001101000001";
        B <= "01101111011110010110010001000110";
        Cin <= '0';
        wait for 1 ns;
        if outs/= "00000000000000000000000000000001" then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_SLT is
end entity testbench_SLT;

architecture behavioral of testbench_SLT is
  signal A,B,S,outs : std_logic_vector (31 downto 0);
  signal Cin,CO,V: std_logic;
  begin
    rippleAdder: entity work.RCA(rtl) port map (A,B,Cin,S,CO,V);
	SetLT: entity work.SLT(rtl) port map (CO,S(31),outs);
      testSequence: process is
      begin
        A <= "11100011100000110001010001101111";--2comp of "00011100011111001110101110010001";
        B <= "01100110111100001100110000111010";
        Cin <= '0';
        wait for 1 ns;
        if outs/= "00000000000000000000000000000001" then 
          ASSERT false
          REPORT " RCA 15-15 error 1"
          SEVERITY failure;
        end if;    
        
      end process testSequence;
end architecture behavioral;
---------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity ANDgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end ANDgate;

architecture rtl of ANDgate is
  begin
    C <= A and B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseAND is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseAND;

architecture rtl of bitwiseAND is
  begin
    andReg: for i in 0 to 31 generate
      cellAND: entity work.ANDgate(rtl) port map(A(i),B(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity ORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end ORgate;

architecture rtl of ORgate is
  begin
    C <= A or B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseOR is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseOR;

architecture rtl of bitwiseOR is
  begin
    orReg: for i in 0 to 31 generate
      cellOR: entity work.ORgate(rtl) port map(A(i),B(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity XORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end XORgate;

architecture rtl of XORgate is
  begin
    C <= A xor B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseXOR is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseXOR;

architecture rtl of bitwiseXOR is
  begin
    xorReg: for i in 0 to 31 generate
      cellXOR: entity work.XORgate(rtl) port map(A(i),B(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity NORgate is
port(
  A   : in std_logic;
  B   : in std_logic;
  C   : out std_logic
);
end NORgate;

architecture rtl of NORgate is
  begin
    C <= A nor B;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity bitwiseNOR is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end bitwiseNOR;

architecture rtl of bitwiseNOR is
  begin
    norReg: for i in 0 to 31 generate
      cellNOR: entity work.NORgate(rtl) port map(A(i),B(i),C(i));
    end generate;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_LogicUnit is
end entity testbench_LogicUnit;

architecture behavioral of testbench_LogicUnit is
  signal A,B, ANDresult, ORresult, XORresult, NORresult: std_logic_vector(31 downto 0);
  begin
    logicAND: entity work.bitwiseAND(rtl) port map(A,B,ANDresult);
      testSequence: process is
      begin
        A <= std_logic_vector(to_signed(0,32));
        B <= std_logic_vector(to_signed(1,32));
        wait for 1 ns;
        if to_integer(signed(ANDresult))/= 0 then 
          ASSERT false
          REPORT " AND 0-1 error"
          SEVERITY failure;
        end if;
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftLeft is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftLeft;

architecture rtl of shiftLeft is
  begin
   C <= to_stdlogicvector(to_bitvector(A) sll (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftRightLogical is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftRightLogical;

architecture rtl of shiftRightLogical is
  begin
   C <= to_stdlogicvector(to_bitvector(A) srl (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity shiftRightArithmetic is
port(
  A   : in std_logic_vector(31 downto 0);
  B   : in std_logic_vector(31 downto 0);
  C   : out std_logic_vector(31 downto 0)
);
end shiftRightArithmetic;

architecture rtl of shiftRightArithmetic is
  begin
   C <= to_stdlogicvector(to_bitvector(A) sra (to_integer(unsigned(B(4 downto 0)))));
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testShift is
end testShift;

architecture behavioral of testShift is
signal A,B,Csl,Csrl,Csra: std_logic_vector(31 downto 0);
	begin
		sl: entity work.shiftLeft(rtl) port map(A,B,Csl);
		lsr: entity work.shiftRightLogical(rtl) port map(A,B,Csrl);
		asr: entity work.shiftRightArithmetic(rtl) port map(A,B,Csra);
		testSequence: process is
		begin
        A <= "10000100010011011110001101001011";
        B <= "01101110001010101010101110010001";
        wait for 1 ns;
        if Csra /= "00000000000001000111001101111000" then 
          ASSERT false
          REPORT " sll 1-1 error"
          SEVERITY failure;
        end if;
      end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity Mux16x1 is
port(
  
  Ins 	 	 : in bus16x32;
  Op		 : in std_logic_vector(3 downto 0);
  Outs  	 : out std_logic_vector(31 downto 0)
);
end Mux16x1;

architecture rtl of Mux16x1 is
  begin
    Outs <= 	Ins(to_integer(unsigned(Op)));
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity testBench_Mux16x1 is
end testBench_Mux16x1;

architecture behavioral of testBench_Mux16x1 is
	signal Ins : bus16x32;
	signal Outs : std_logic_vector(31 downto 0);
	signal Op: std_logic_vector (3 downto 0);
  begin
	muxer: entity work.Mux16x1(rtl) port map(Ins,Op,Outs);
    testSequence: process is
      begin
        Op <= "0000";
		Ins(0) <= "11111111111111111111111111111111";
        wait for 1 ns;
        if Outs/= "11111111111111111111111111111111" then 
          ASSERT false
          REPORT " Mux 0000 error"
          SEVERITY failure;
        end if;      
		
		Op <= "0100";
		Ins(4) <= "11111111111111111111111111111111";
        wait for 1 ns;
        if Outs/= "11111111111111111111111111111111" then 
          ASSERT false
          REPORT " Mux 0100 error"
          SEVERITY failure;
        end if;      		
        end process testSequence;
end architecture behavioral;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity ALU_RCA is
port(
  Clk : in std_logic;
  Reset : in std_logic;
  A : in std_logic_vector(31 downto 0);
  B : in std_logic_vector(31 downto 0);
  Op : in std_logic_vector(3 downto 0);
  Outs : out std_logic_vector(31 downto 0)
);
end ALU_RCA;

architecture rtl of ALU_RCA is
signal CO,V 		: std_logic;
signal sum			: std_logic_vector(31 downto 0);
signal muxIns 		: bus16x32;
signal muxOuts		: std_logic_vector(31 downto 0);
signal in_pipeline 	: in_pipeline_stage;
signal outBus		: bus16x32;
signal out_pipeline : out_pipeline_stage;
begin
	rippleAdder0	: entity work.RCA(rtl) 					port map(in_pipeline.A,in_pipeline.B,'0',sum,CO,V);
	logicAND		: entity work.bitwiseAND(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(4));
	logicOR			: entity work.bitwiseOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(5));
	logicNOR		: entity work.bitwiseNOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(6));
	logicXOR		: entity work.bitwiseXOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(7));
	leftshift		: entity work.shiftLeft(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(8));
	rightshiftlo	: entity work.shiftRightLogical(rtl) 	port map(in_pipeline.A,in_pipeline.B,outBus(10));
	rightshiftar	: entity work.shiftRightArithmetic(rtl) port map(in_pipeline.A,in_pipeline.B,outBus(11));
	sltop			: entity work.SLT(rtl) 					port map(sum(31),V,outBus(14));
	sltuop			: entity work.SLTU(rtl) 				port map(CO,outBus(15));
	muxer			: entity work.Mux16x1(rtl) 				port map(out_pipeline.outLine,out_pipeline.Op,muxOuts);
	
	outBus(0) <= sum;
	outBus(1) <= sum;
	outBus(2) <= sum;
	outBus(3) <= sum;
	outBus(9)  <= (31 downto 0 => '0');
	outBus(12) <= (31 downto 0 => '0');
	outBus(13) <= (31 downto 0 => '0');
	
	seq_process : process (Clk,Reset) is
	begin
		if rising_edge(Clk) and Reset = '1' then
			if Op = "0010" or Op = "0011" then
				in_pipeline.A <= A;
				in_pipeline.B <= std_logic_vector(unsigned(not B) + 1);
			elsif Op = "1110" or Op = "1111" then
				in_pipeline.A <= std_logic_vector(unsigned(not A) + 1);
				in_pipeline.B <= B;
			else
				in_pipeline.A <= A;
				in_pipeline.B <= B;
			end if;
		in_pipeline.Op <= Op;
		
		out_pipeline.outLine <= outBus;
		out_pipeline.Op 	 <= in_pipeline.Op ;
		
		Outs <= muxOuts;
		end if;
	end process seq_process;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity testbecnch_ALU_RCA is
end entity testbecnch_ALU_RCA;

architecture behavioral of testbecnch_ALU_RCA is
constant Size    : integer := 1100;
type Operand_array is array (Size downto 0) of std_logic_vector(31 downto 0);
type OpCode_array is array (Size downto 0) of std_logic_vector(3 downto 0);
  
signal clk,reset 			: std_logic;
signal A,B,outs,expOuts 	: std_logic_vector (31 downto 0);
signal Op					: std_logic_vector (3 downto 0);


  -----------------------------------------------------------------------------
  -- Functions
  -----------------------------------------------------------------------------
  function bin ( myChar : character) return std_logic is
    variable bin : std_logic;
  begin
    case myChar is
      when '0' => bin := '0';
      when '1' => bin := '1';
      when 'x' => bin := '0';
      when others => assert (false) report "no binary character read" severity failure;
    end case;
    return bin;
  end bin;
  
  function loadOperand (fileName : string) return Operand_array is
    file objectFile : text open read_mode is fileName;
    variable memory : Operand_array;
    variable L      : line;
    variable index  : natural := 0;
    variable myChar : character;
  begin
    while not endfile(objectFile) loop
      readline(objectFile, L);
      for i in 31 downto 0 loop
        read(L, myChar);
        memory(index)(i) := bin(myChar);
      end loop;
      index := index + 1;
    end loop;
    return memory;
  end loadOperand;


  function loadOpCode (fileName : string) return OpCode_array is
    file objectFile : text open read_mode is fileName;
    variable memory : OpCode_array;
    variable L      : line;
    variable index  : natural := 0;
    variable myChar : character;
  begin
    while not endfile(objectFile) loop
      readline(objectFile, L);
      for i in 3 downto 0 loop
        read(L, myChar);
        memory(index)(i) := bin(myChar);
      end loop;
      index := index + 1;
    end loop;
    return memory;
  end loadOpCode;
  
begin
	rca_alu: entity work.ALU_RCA(rtl) port map (clk,reset,A,B,Op,outs);
	clk_gen: process is
	begin
		clk <= '0';
		wait for 0.05 us;
		clk <= '1';
		wait for 0.05 us;
	end process clk_gen;
	
	test_sequence : process is
	variable tv_A,tv_B,tv_expectedOuts : Operand_array;
	variable tv_Op : OpCode_array;
	begin
	
	tv_A := loadOperand("C:\data\tv\A.tv");
	tv_B := loadOperand("C:\data\tv\B.tv");
	tv_expectedOuts := loadOperand("C:\data\tv\ExpectOut.tv");
	tv_Op := loadOpCode("C:\data\tv\Op.tv");
	
	for i in 0 to 999 loop	
		A 	<= tv_A(i);
		B 	<= tv_B(i);
		Op  <= tv_Op(i);
		expOuts <= tv_expectedOuts(i); 
		reset  <= '1';
		
		wait for 0.3 us;
		if outs/= expOuts then 
          ASSERT false
          REPORT " ALU_RCA TC" &integer'image(i) &"error"
          SEVERITY failure;
        end if;
	end loop;	
	
	end process test_sequence;
end architecture behavioral;
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity ALU_SKL is
port(
  Clk : in std_logic;
  Reset : in std_logic;
  A : in std_logic_vector(31 downto 0);
  B : in std_logic_vector(31 downto 0);
  Op : in std_logic_vector(3 downto 0);
  Outs : out std_logic_vector(31 downto 0)
);
end ALU_SKL;

architecture rtl of ALU_SKL is
component sklansky is
   port(
	OpA	: in	std_logic_vector(31 downto 0);
	OpB	: in	std_logic_vector(31 downto 0);
	Cin	: in	std_logic;
	Result	: out	std_logic_vector(31 downto 0);
	Cout	: out	std_logic;
	V		: out	std_logic -- modification to include overflow logic
	);
end component;

signal CO,V 		: std_logic;
signal sum			: std_logic_vector(31 downto 0);
signal muxIns 		: bus16x32;
signal muxOuts		: std_logic_vector(31 downto 0);
signal in_pipeline 	: in_pipeline_stage;
signal outBus		: bus16x32;
signal out_pipeline : out_pipeline_stage;
begin
	rippleAdder0	: entity work.sklansky(rtl)				port map(in_pipeline.A,in_pipeline.B,'0',sum,CO,V);
	logicAND		: entity work.bitwiseAND(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(4));
	logicOR			: entity work.bitwiseOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(5));
	logicNOR		: entity work.bitwiseNOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(6));
	logicXOR		: entity work.bitwiseXOR(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(7));
	leftshift		: entity work.shiftLeft(rtl) 			port map(in_pipeline.A,in_pipeline.B,outBus(8));
	rightshiftlo	: entity work.shiftRightLogical(rtl) 	port map(in_pipeline.A,in_pipeline.B,outBus(10));
	rightshiftar	: entity work.shiftRightArithmetic(rtl) port map(in_pipeline.A,in_pipeline.B,outBus(11));
	sltop			: entity work.SLT(rtl) 					port map(sum(31),V,outBus(14));
	sltuop			: entity work.SLTU(rtl) 				port map(CO,outBus(15));
	muxer			: entity work.Mux16x1(rtl) 				port map(out_pipeline.outLine,out_pipeline.Op,muxOuts);
	
	outBus(0) <= sum;
	outBus(1) <= sum;
	outBus(2) <= sum;
	outBus(3) <= sum;
	outBus(9)  <= (31 downto 0 => '0');
	outBus(12) <= (31 downto 0 => '0');
	outBus(13) <= (31 downto 0 => '0');
	
	seq_process : process (Clk,Reset) is
	begin
		if rising_edge(Clk) and Reset = '1' then
			if Op = "0010" or Op = "0011" then
				in_pipeline.A <= A;
				in_pipeline.B <= std_logic_vector(unsigned(not B) + 1);
			elsif Op = "1110" or Op = "1111" then
				in_pipeline.A <= std_logic_vector(unsigned(not A) + 1);
				in_pipeline.B <= B;
			else
				in_pipeline.A <= A;
				in_pipeline.B <= B;
			end if;
		in_pipeline.Op <= Op;
		
		out_pipeline.outLine <= outBus;
		out_pipeline.Op 	 <= in_pipeline.Op ;
		
		Outs <= muxOuts;
		end if;
	end process seq_process;
end architecture rtl;
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.numeric_std.all;
use work.custom_types.all;

entity testbecnch_ALU_SKL is
end entity testbecnch_ALU_SKL;

architecture behavioral of testbecnch_ALU_SKL is
constant Size    : integer := 1100;
type Operand_array is array (Size downto 0) of std_logic_vector(31 downto 0);
type OpCode_array is array (Size downto 0) of std_logic_vector(3 downto 0);
  
signal clk,reset 			: std_logic;
signal A,B,outs,expOuts 	: std_logic_vector (31 downto 0);
signal Op					: std_logic_vector (3 downto 0);


  -----------------------------------------------------------------------------
  -- Functions
  -----------------------------------------------------------------------------
  function bin ( myChar : character) return std_logic is
    variable bin : std_logic;
  begin
    case myChar is
      when '0' => bin := '0';
      when '1' => bin := '1';
      when 'x' => bin := '0';
      when others => assert (false) report "no binary character read" severity failure;
    end case;
    return bin;
  end bin;
  
  function loadOperand (fileName : string) return Operand_array is
    file objectFile : text open read_mode is fileName;
    variable memory : Operand_array;
    variable L      : line;
    variable index  : natural := 0;
    variable myChar : character;
  begin
    while not endfile(objectFile) loop
      readline(objectFile, L);
      for i in 31 downto 0 loop
        read(L, myChar);
        memory(index)(i) := bin(myChar);
      end loop;
      index := index + 1;
    end loop;
    return memory;
  end loadOperand;


  function loadOpCode (fileName : string) return OpCode_array is
    file objectFile : text open read_mode is fileName;
    variable memory : OpCode_array;
    variable L      : line;
    variable index  : natural := 0;
    variable myChar : character;
  begin
    while not endfile(objectFile) loop
      readline(objectFile, L);
      for i in 3 downto 0 loop
        read(L, myChar);
        memory(index)(i) := bin(myChar);
      end loop;
      index := index + 1;
    end loop;
    return memory;
  end loadOpCode;
  
begin
	rca_alu: entity work.ALU_SKL(rtl) port map (clk,reset,A,B,Op,outs);
	clk_gen: process is
	begin
		clk <= '0';
		wait for 0.05 us;
		clk <= '1';
		wait for 0.05 us;
	end process clk_gen;
	
	test_sequence : process is
	variable tv_A,tv_B,tv_expectedOuts : Operand_array;
	variable tv_Op : OpCode_array;
	begin
	
	tv_A := loadOperand("C:\data\tv\A.tv");
	tv_B := loadOperand("C:\data\tv\B.tv");
	tv_expectedOuts := loadOperand("C:\data\tv\ExpectOut.tv");
	tv_Op := loadOpCode("C:\data\tv\Op.tv");
	
	for i in 0 to 1000 loop	
		A 	<= tv_A(i);
		B 	<= tv_B(i);
		Op  <= tv_Op(i);
		expOuts <= tv_expectedOuts(i); 
		reset  <= '1';
		
		wait for 0.3 us;
		if outs/= expOuts then 
          ASSERT false
          REPORT " ALU_RCA TC" &integer'image(i) &"error"
          SEVERITY failure;
        end if;
	end loop;	
	
	end process test_sequence;
end architecture behavioral;
-----------------------------------------------------------------------------